6000 // The local APIC manages internal (non-I/O) interrupts.
6001 // See Chapter 8 & Appendix C of Intel processor manual volume 3.
6002 
6003 #include "types.h"
6004 #include "defs.h"
6005 #include "traps.h"
6006 #include "mmu.h"
6007 #include "x86.h"
6008 
6009 // Local APIC registers, divided by 4 for use as uint[] indices.
6010 #define ID      (0x0020/4)   // ID
6011 #define VER     (0x0030/4)   // Version
6012 #define TPR     (0x0080/4)   // Task Priority
6013 #define EOI     (0x00B0/4)   // EOI
6014 #define SVR     (0x00F0/4)   // Spurious Interrupt Vector
6015   #define ENABLE     0x00000100   // Unit Enable
6016 #define ESR     (0x0280/4)   // Error Status
6017 #define ICRLO   (0x0300/4)   // Interrupt Command
6018   #define INIT       0x00000500   // INIT/RESET
6019   #define STARTUP    0x00000600   // Startup IPI
6020   #define DELIVS     0x00001000   // Delivery status
6021   #define ASSERT     0x00004000   // Assert interrupt (vs deassert)
6022   #define DEASSERT   0x00000000
6023   #define LEVEL      0x00008000   // Level triggered
6024   #define BCAST      0x00080000   // Send to all APICs, including self.
6025   #define BUSY       0x00001000
6026   #define FIXED      0x00000000
6027 #define ICRHI   (0x0310/4)   // Interrupt Command [63:32]
6028 #define TIMER   (0x0320/4)   // Local Vector Table 0 (TIMER)
6029   #define X1         0x0000000B   // divide counts by 1
6030   #define PERIODIC   0x00020000   // Periodic
6031 #define PCINT   (0x0340/4)   // Performance Counter LVT
6032 #define LINT0   (0x0350/4)   // Local Vector Table 1 (LINT0)
6033 #define LINT1   (0x0360/4)   // Local Vector Table 2 (LINT1)
6034 #define ERROR   (0x0370/4)   // Local Vector Table 3 (ERROR)
6035   #define MASKED     0x00010000   // Interrupt masked
6036 #define TICR    (0x0380/4)   // Timer Initial Count
6037 #define TCCR    (0x0390/4)   // Timer Current Count
6038 #define TDCR    (0x03E0/4)   // Timer Divide Configuration
6039 
6040 volatile uint *lapic;  // Initialized in mp.c
6041 
6042 static void
6043 lapicw(int index, int value)
6044 {
6045   lapic[index] = value;
6046   lapic[ID];  // wait for write to finish, by reading
6047 }
6048 
6049 
6050 void
6051 lapicinit(int c)
6052 {
6053   cprintf("lapicinit: %d 0x%x\n", c, lapic);
6054   if(!lapic)
6055     return;
6056 
6057   // Enable local APIC; set spurious interrupt vector.
6058   lapicw(SVR, ENABLE | (T_IRQ0 + IRQ_SPURIOUS));
6059 
6060   // The timer repeatedly counts down at bus frequency
6061   // from lapic[TICR] and then issues an interrupt.
6062   // If xv6 cared more about precise timekeeping,
6063   // TICR would be calibrated using an external time source.
6064   lapicw(TDCR, X1);
6065   lapicw(TIMER, PERIODIC | (T_IRQ0 + IRQ_TIMER));
6066   lapicw(TICR, 10000000);
6067 
6068   // Disable logical interrupt lines.
6069   lapicw(LINT0, MASKED);
6070   lapicw(LINT1, MASKED);
6071 
6072   // Disable performance counter overflow interrupts
6073   // on machines that provide that interrupt entry.
6074   if(((lapic[VER]>>16) & 0xFF) >= 4)
6075     lapicw(PCINT, MASKED);
6076 
6077   // Map error interrupt to IRQ_ERROR.
6078   lapicw(ERROR, T_IRQ0 + IRQ_ERROR);
6079 
6080   // Clear error status register (requires back-to-back writes).
6081   lapicw(ESR, 0);
6082   lapicw(ESR, 0);
6083 
6084   // Ack any outstanding interrupts.
6085   lapicw(EOI, 0);
6086 
6087   // Send an Init Level De-Assert to synchronise arbitration ID's.
6088   lapicw(ICRHI, 0);
6089   lapicw(ICRLO, BCAST | INIT | LEVEL);
6090   while(lapic[ICRLO] & DELIVS)
6091     ;
6092 
6093   // Enable interrupts on the APIC (but not on the processor).
6094   lapicw(TPR, 0);
6095 }
6096 
6097 
6098 
6099 
6100 int
6101 cpunum(void)
6102 {
6103   // Cannot call cpu when interrupts are enabled:
6104   // result not guaranteed to last long enough to be used!
6105   // Would prefer to panic but even printing is chancy here:
6106   // almost everything, including cprintf and panic, calls cpu,
6107   // often indirectly through acquire and release.
6108   if(readeflags()&FL_IF){
6109     static int n;
6110     if(n++ == 0)
6111       cprintf("cpu called from %x with interrupts enabled\n",
6112         __builtin_return_address(0));
6113   }
6114 
6115   if(lapic)
6116     return lapic[ID]>>24;
6117   return 0;
6118 }
6119 
6120 // Acknowledge interrupt.
6121 void
6122 lapiceoi(void)
6123 {
6124   if(lapic)
6125     lapicw(EOI, 0);
6126 }
6127 
6128 // Spin for a given number of microseconds.
6129 // On real hardware would want to tune this dynamically.
6130 void
6131 microdelay(int us)
6132 {
6133 }
6134 
6135 #define IO_RTC  0x70
6136 
6137 // Start additional processor running bootstrap code at addr.
6138 // See Appendix B of MultiProcessor Specification.
6139 void
6140 lapicstartap(uchar apicid, uint addr)
6141 {
6142   int i;
6143   ushort *wrv;
6144 
6145   // "The BSP must initialize CMOS shutdown code to 0AH
6146   // and the warm reset vector (DWORD based at 40:67) to point at
6147   // the AP startup code prior to the [universal startup algorithm]."
6148   outb(IO_RTC, 0xF);  // offset 0xF is shutdown code
6149   outb(IO_RTC+1, 0x0A);
6150   wrv = (ushort*)(0x40<<4 | 0x67);  // Warm reset vector
6151   wrv[0] = 0;
6152   wrv[1] = addr >> 4;
6153 
6154   // "Universal startup algorithm."
6155   // Send INIT (level-triggered) interrupt to reset other CPU.
6156   lapicw(ICRHI, apicid<<24);
6157   lapicw(ICRLO, INIT | LEVEL | ASSERT);
6158   microdelay(200);
6159   lapicw(ICRLO, INIT | LEVEL);
6160   microdelay(100);    // should be 10ms, but too slow in Bochs!
6161 
6162   // Send startup IPI (twice!) to enter bootstrap code.
6163   // Regular hardware is supposed to only accept a STARTUP
6164   // when it is in the halted state due to an INIT.  So the second
6165   // should be ignored, but it is part of the official Intel algorithm.
6166   // Bochs complains about the second one.  Too bad for Bochs.
6167   for(i = 0; i < 2; i++){
6168     lapicw(ICRHI, apicid<<24);
6169     lapicw(ICRLO, STARTUP | (addr>>12));
6170     microdelay(200);
6171   }
6172 }
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